1. Design the state Moore machine given in Figure 6. The state machine is positive edge...

 

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1. Design the state Moore machine given in Figure 6. The state machine is positive edge triggered. Include a reset to your state machine. Simulate and verify your results with a test bench file. SI OUT-2 S2 S4 OUT-4 OUT-3 S3 OUT-1 Figure 6 2. Implement the state machine on the Spartan 3E FPGA board. 1. Design the state Moore machine given in Figure 6. The state machine is positive edge triggered. Include a reset to your state machine. Simulate and verify your results with a test bench file. SI OUT-2 S2 S4 OUT-4 OUT-3 S3 OUT-1 Figure 6 2. Implement the state machine on the Spartan 3E FPGA board.