Failed Tests

$7$: Program simulates two instructions "addi $$3,$

$$3,8"$ and $"$Iw $$3,8($$$4)"$ correctly $(0/10)$

$8$: Program simulates two instructions "addi $$2,$

$$2,16"$ and $"$sw $$2,8($$$2)"$ correctly $(0/10)$

$9$: Program simulates two instructions "addi $$2,$

$$2,16"$ then "beq $$3,$$$4,20"$ correctly $(0//10)$

$10$: Program simulates a set of instruction "addi

$$7,$ $$7,5",$ "addi $$3,$ $$3,1",$ and "bne $$7,$ $$3,-8"$

correctly $(0/20)$

Here is my code this is in python $```$

import argparse

# Set up command$-$line argument parsing

parser $=$ argparse.ArgumentParser$($description$=$"Simulate single$-$cycle MIPS datapath $($beta version$)")$

parser.add$\_$argument$("--$program", required$=$True, help$=$"Path to machine$-$language input file"$)$

parser.add$\_$argument$("--$memory", required$=$True, help$=$"Path to memory file"$)$

args $=$ parser.parse$\_$args$()$

program$\_$file$\_$path $=$ args.program

memory$\_$file$\_$path $=$ args.memory

# File paths for output

control$\_$output$\_$file$\_$path $=$ 'out$\_$control.txt$\text{'}$

registers$\_$output$\_$file$\_$path $=$ 'out$\_$registers.txt$\text{'}$

memory$\_$output$\_$file$\_$path $=$ 'out$\_$memory.txt$\text{'}$

# Initialize registers, program counter, and memory

registers $=[0]*8$

pc$\}=6553$

memory $=[]$

# Load memory from file

with open$($memory$\_$file$\_$path, $\text{'}$r$\text{'})$ as f:

memory $=[$int$($line$.$strip$())$ for line in f$.$readlines$()]$

# Define control signals and ALU operations

CONTROL$\_$SIGNALS $=\{$

'add': $\text{'}1001000100\text{'},$

'sub': $\text{'}1001000100\text{'},$

'addi': $\text{'}0101000000\text{'},$

$\text{'}$lw$\text{'}$: $\text{'}0111100000\text{'},$

$\text{'}$SW$\text{'}$: $\text{'}$X$1$X$0010000\text{'},$

'beq': $\text{'}$X$0$X$0001011\text{'},$

'bne': $\text{'}$x$0$x$0001110\text{'}$

$\}$

ALU$\_$OPCODES $=\{$

'add': lambda x$,$ y: x $+$ y$,$

'sub': lambda x$,$ y: x $-$ y$,$

$``````$

'addi': lambda x$,$ imm: x $+$ imm

$\}$

# Parse an instruction to get opcode and fields

def parse$\_$instruction$($instruction$)$:

opcode $=$ instruction$[0$:$6]$

rs $=$ int$($instruction$[6$:$11],2)$

rt $=$ int$($instruction$[11$:$16],2)$

rd $=$ int$($instruction$[16$:$21],2)$

immediate $=$ int$($instruction$[16$:$],2)$ if instruction$[16]==\text{'}0\text{'}$ else int$($instruction$[16$:$],2)-(116)$

funct $=$ instruction$[26$:$]$

return opcode, rs$,$ rt$,$ rd$,$ immediate, funct

# Execute an instruction

def execute$\_$instruction$($instruction$)$:

global pc$,$ registers, memory

opcode, rs$,$ rt$,$ rd$,$ immediate, funct $=$ parse$\_$instruction$($instruction$)$

zero $=0$ # Zero flag for branch instructions

if opcode $==\text{'}000000\text{'}$: # R$-$type instructions

if funct $==\text{'}100000\text{'}$: # add

control$\_$signals $=$ CONTROL$\_$SIGNALS$[\text{'}$add$\text{'}]$

registers$[$rd$]=$ ALU$\_$OPCODES$[\text{'}$add$\text{'}]($registers$[$rs$],$ registers$[$rt$])$

elif funct $==\text{'}100010\text{'}$: # sub

control$\_$signals $=$ CONTROL$\_$SIGNALS$[\text{'}$sub$\text{'}]$

registers$[$rd$]=$ ALU$\_$OPCODES$[\text{'}$sub$\text{'}]($registers$[$rs$],$ registers$[$rt$])$

else:

return None, None

elif opcode $==\text{'}001000\text{'}$: # addi

control$\_$signals $=$ CONTROL$\_$SIGNALS$[\text{'}$addi$\text{'}]$

registers$[$rt$]=$ ALU$\_$OPCODES$[\text{'}$addi$\text{'}]($registers$[$rs$],$ immediate$)$

elif opcode $==\text{'}100011\text{'}$: # lw

control$\_$signals $=$ CONTROL$\_$SIGNALS$[\text{'}$lw$\text{'}]$

address $=$ registers$[$rs$]+$ immediate

if address $<0$ or address $>=$ len$($memory$)$: # Validate address

$``````$

return control$\_$signals, "segfault"

value $=$ memory$[$address$]$

if value $>=(1<<31)$: # Sign$-$extend $32-$bit value

value $-=(1<<32)$

registers$[$rt$]=$ value

elif opcode $==\text{'}101011\text{'}$: # sw

control$\_$signals $=$ CONTROL$\_$SIGNALS$[\text{'}$sw$\text{'}]$

address $=$ registers$[$rs$]+$ immediate

if address $<0$ or address $>=$ len$($memory$)$: # Validate address

return control$\_$signals, "segfault"

memory$[$address$]=$ registers$[$rt$]$

elif opcode $==\text{'}000100\text{'}$: # beq

control$\_$signals $=$ CONTROL$\_$SIGNALS$[\text{'}$beq$\text{'}]$

zero $=1$ if registers$[$rs$]==$ registers$[$rt$]$ else $0$

branch$\_$offset $=$ immediate $<<2$ # Shift left by $2$ for byte offset

if zero:

pc $+=$ branch$\_$offset

else:

pc $+=4$

elif opcode $==\text{'}000101\text{'}$: # bne

control$\_$signals $=$ CONTROL$\_$SIGNALS$[\text{'}$bne$\text{'}]$

zero $=1$ if registers$[$rs$]!=$ registers$[$rt$]$ else $0$

branch$\_$offset $=$ immediate $<<2$ # Shift left by $2$ for byte offset

if zero:

pc $+=$ branch$\_$offset

else:

pc $+=4$

else:

return None, None

pc $+=4$

return control$\_$signals $+$ str$($zero$),$ None

# Ensure control signal is exactly $10$ bits

def pad control signal$($signal$)$:

$``````$

return signal$[$:$10]$

# Simulate instructions

def simulate$($instructions$)$:

instruction$\_$memory $=[($pc $+$ i $*4,$ line.strip$())$ for i$,$ line in enumerate$($instructions$)]$

with open$($control$\_$output$\_$file$\_$path, $\text{'}$w$\text{'})$ as control$\_$file, $\backslash$

open$($registers$\_$output$\_$file$\_$path, $\text{'}$w$\text{'})$ as registers$\_$file:

registers$\_$file.write$($f$"\{$pc$\}|\{\text{'}|\text{'}.$join$($map$($str$,$ registers$))\}$

$")$

for current$\_$pc$,$ instruction in instruction$\_$memory:

if pc $<65536$ or pc $>=65536+$ len$($instructions$)*4$:

control$\_$file.write$("!!!$ Segmentation Fault $!!!$

$")$

registers$\_$file.write$("!!!$ Segmentation Fault $!!!$

$")$

return

control$\_$signals, fault $=$ execute$\_$instruction$($instruction$)$

if fault $==$ "segfault":

control$\_$file.write$("!!!$ Segmentation Fault $!!!$

$")$

registers$\_$file.write$("!!!$ Segmentation Fault $!!!$

$")$

return

control$\_$signals $=$ pad$\_$control$\_$signal$($control$\_$signals$)$

control$\_$file.write$($f$"\{$control$\_$signals$\}$

$")$

registers$\_$file.write$($f$"\{$pc$\}|\{\text{'}|\text{'}.$join$($map$($str$,$ registers$))\}$

$")$

with open$($memory$\_$output$\_$file$\_$path, $\text{'}$w$\text{'})$ as memory$\_$file:

memory$\_$file.writelines$($f$"\{$word$\}$

$"$ for word in memory$)$

# Load instructions from the program file

with open$($program$\_$file$\_$path, $\text{'}$r$\text{'})$ as f:

instructions $=$ f$.$readlines$()$

# Run the simulat Failed Tests

$7$: Program simulates two instructions "addi $\backslash$$$3,\backslash (\backslash$$ $3,8\backslash )"$ and $"$Iw $\backslash$$$3,8(\backslash$$$4)"$ correctly