Fig. $4(3)$ is a $742809-$bit parity gencrator, and Fig. $4(b)$ is a XOR gate with Iwo fan$-$in$.$

$($a$)$ Please design a $12-$bit parity generator using two $74280($note: you cannot use other logic gates$).$ Your circuit should clearly mark the positions of $12$ inputs. $(5\%)$

$($b$)$ Redo $($a$)$ by using one $74280$ and three XOR gates in Fig. $4($b$).(5\%)$

$($a$)$

XOR gate

$($b$)$

Fig. $4.74280$ parity genitor and XOR gate.