Figure $1$ shows a $32-$bit bidirectional shift regiters with its signal description

Data $=$ The input Data is equal to $1[$logic high$].$ This data should be shifted right or left

DIR $=$ Shift Direction Control: For DIR $=0[$Shift Left$]$ and DIR $=1[$shift Right$]$

$CL{K}_{?}=$ Clock signal, any clock can be used from $10$ kHz to $1$ MHz

SHC $=$ Multi$-$bit Shift control signal: If SHC $=0[1-$bit shift only$],$ if SHC $=1[2-$bit, $4-$bit, or $8-$bit shift based on students design choice$]$

Figure $1.32-$bit bidirectional shift register with multi$-$bit shift control

Use the $32-$bit bidirectional shift registers. Each group should choose the adaptive$/$multiple bit shifting by themselves from either $2-$bit, $4-$bit, or $8-$bits.

Write the VHDL code to describe using a suitable design style.

Simulate your design. First you should write the code for single bit shifting and show the simulation result. Then you should include the multiple bit shifting and show the simulation result.