Estimate (a) the current lo (b) the delay in a l-to-0 transition at one of the...

    

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Estimate (a) the current lo (b) the delay in a l-to-0 transition at one of the inputs of GATE I appearing as an effect at the output of GATE 5. (e) the total power consumed by the circuit in a quiescent state. Use the information given in the table at the end of this TMA FIGURE 1 shows an ALS circuit lOL FIGURE 1 Estimate (a) the current lo (b) the delay in a 1-to-0 transition at one of the inputs of GATE I appearing as an effect at the output of GATE 5. (c) the total power consumed by the circuit in a quiescent state. Use the information given in the table at the end of this TMA Performance Specifications Typical Single-Gate Perfomance Specifications Speed-Power Propagation Power Product Fumily Delay (ms) Dissipation (mW) pW-s (picowatt-seconds) 74 10 10 100 74S 20 60 74LS 9. 2 18 74ALS 4 4. 74F 2.7 %3D 1 at 1 MHz 15 at I MHz 4000B (CMOS) 105 105 74HC (CMOS) 10 15 INTERFACING LOGIC FAMILIES Warst-Case Values for Interfacing Considerations for V of 5.0 V ly Parameter 4000B CMOS 74HCMOS 74HCTMOS 74TTL 74LSTTL 74ALSTTL VIn (min) (V) VI, (max) (V) Von (min) (V) VoL (max) (V) 3.33 3.5 2.0 2.0 2.0 2.0 1.67 10 0.8 0.8 0.8 0.8 4.95 4.9 4.9 2.4 2.7 2.7 0.05 0.1 0.1 0.4 04 0.4 l (max) (HA) 40 20 20 (max) (HA) *loH (max) (mA) *lo (max) (mA) -1 -1600 400 -100 0.51 -0.4 -0.4 0.4 0.51 16 8 *The convenion is that current flowing into a gate terminal is positive and that flowing out is negative. Estimate (a) the current lo (b) the delay in a l-to-0 transition at one of the inputs of GATE I appearing as an effect at the output of GATE 5. (e) the total power consumed by the circuit in a quiescent state. Use the information given in the table at the end of this TMA FIGURE 1 shows an ALS circuit lOL FIGURE 1 Estimate (a) the current lo (b) the delay in a 1-to-0 transition at one of the inputs of GATE I appearing as an effect at the output of GATE 5. (c) the total power consumed by the circuit in a quiescent state. Use the information given in the table at the end of this TMA Performance Specifications Typical Single-Gate Perfomance Specifications Speed-Power Propagation Power Product Fumily Delay (ms) Dissipation (mW) pW-s (picowatt-seconds) 74 10 10 100 74S 20 60 74LS 9. 2 18 74ALS 4 4. 74F 2.7 %3D 1 at 1 MHz 15 at I MHz 4000B (CMOS) 105 105 74HC (CMOS) 10 15 INTERFACING LOGIC FAMILIES Warst-Case Values for Interfacing Considerations for V of 5.0 V ly Parameter 4000B CMOS 74HCMOS 74HCTMOS 74TTL 74LSTTL 74ALSTTL VIn (min) (V) VI, (max) (V) Von (min) (V) VoL (max) (V) 3.33 3.5 2.0 2.0 2.0 2.0 1.67 10 0.8 0.8 0.8 0.8 4.95 4.9 4.9 2.4 2.7 2.7 0.05 0.1 0.1 0.4 04 0.4 l (max) (HA) 40 20 20 (max) (HA) *loH (max) (mA) *lo (max) (mA) -1 -1600 400 -100 0.51 -0.4 -0.4 0.4 0.51 16 8 *The convenion is that current flowing into a gate terminal is positive and that flowing out is negative.