Figure 3.1 shows the Verilog HDL code with several syntax errors. Determine the errors and rewrite the Verilog HDL code with the correct syntax. (Rajah 3.1 menunjukkan kod Verilog HDL bersama dengan beberapa kesalahan nahu. Tentukan kesalahannya dan tulis semula kod Verilog HDL bersama dengan nahi yang betul.] (6 Marks/ Markah) module examl (ini, sel); input [1:0] inl; input [2:0] sel; output (15:0] out2; reg (7:0) select; /* address decoder / always @ (sel); case (sel) 3'b000 : select 8'b00000001: 3'b001 : select = 8'b00000010; 3'1010 : select = 7'500000100; 3'b011 : select = 8'b00001000: 3'5100: select = 8'b00010000; 3'b100 : select 8'b00100000; 3'b110 : select 8'501000000; 3'blll : select 8'b10000000 end; assign out2[1:0) = inl & select(0); assign out2 [3:2] inl & select[1]; assign out 2 [5:4] inl & select [2]; assign out2 [7:6] = inl be select [3]; assign out2[9;8] = inl & select [4]; assign out2[11:10] inl & select [5]; assign out2[13:12] ini & select [6]; assign out2 [15:14] ini & select[7]; end