Figure 6 shows a 7-segment decoder module that has the two-bit input c1c0. This decoder produces seven outputs that are used to display a character on a 7-segment display. Table 1 lists the characters that should be displayed for each valuation of c1c0. To keep the design simple, only three characters are included in the table (plus the blank character, which is selected for codes 11). The seven segments in the display are identified by the indices 0 to 6 shown in the figure. Each segment is illuminated by driving it to the logic value 0. You are to write a VHDL entity that implements logic functions that represent circuits needed to activate each of the seven segments. Use only simple VHDL assignment statements in your code to specify each logic function using a Boolean expression.

Perform the following steps: 1. Create a new Quartus II project for your circuit. 2. Create a VHDL entity for the 7-segment decoder. Connect the c 1c 0 inputs to switches SW1 0, and connect the outputs of the decoder to the HEX0 display on the DE10-Lite board. The segments in this display are called HEX00, HEX01, . . ., HEX06, corresponding to Figure 6. You should declare the 7-bit port HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6); in your VHDL code so that the names of these outputs match the corresponding names in the DE10-Lite User Manual and the DE10_Lite_pin_assignments.qsffile. 3. After making the required DE10-Lite board pin assignments, compile the project. 4. Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by toggling the SW1 0 switches and observing the 7-segment display

ciCo Character 01 10 Table 1. Character codes