Part IV Perform the following steps:

Write Verilog code for your $7-$segment decoder. Connect the $c_1{c}_0$ inputs to switches $S{W}_{1-0},$ and connect

the outputs of the decoder to the HEXO display on the DE$1-$SoC board. The segments in this display are

called $HEx{O}_0,HEx{O}_1,$dots,$HEx{O}_6,$ corresponding to Figure $6.$

A top.v file is provided as part of the design files for this exercise, for use with the DESim tool. Compiling

and simulating your $7-$segment decoder with DESim is a good way to see how the $7-$segment displays will

look when your circuit is implemented in a DE$1-$SoC board. To use the top.v file directly, declare your

Verilog module as:

module part$4($SW$,$ LEDR, HEX$0)$;

input $[1$:$0]$ SW; $//$ toggle switches

output $[9$:$0]$ LEDR; $//$ red LEDs

output $[6$:$0]$ HEX$0$; $//7-$seg display

$...$

endmodule

After you have finished testing your Verilog code using simulation, create a Quartus project for your circuit.

Make sure to include all required pin assignments in the project.

Compile your project and then download the resulting circuit into the FPGA chip. Test the functionality of

the circuit by toggling the $S{W}_{1-0}$ switches and observing the $7-$segment display.

Figure $6$ depicts a $7-$segment decoder module that has the two$-$bit input $c_1{c}_0.$ This decoder produces seven outputs

that are used to display a character on a $7-$segment display. Table $1$ lists the characters that should be displayed

for each valuation of $c_1{c}_0.$ Three characters are included plus the 'blank' character, which is selected for code $11.$

The seven segments in the display are identified by the indices $0$ to $6$ shown in the figure. Each segment is

illuminated by driving it to the logic value $0.$ You are to write a Verilog module that implements a logic function

for each of the seven segments. Use only simple Verilog assign statements in your code to specify each logic

function using a Boolean expression.

Figure $6$: A $7-$segment decoder.

Table $1.$ Character codes.