Fill in missing code where its highlighted

$($Q$1)$ Consider a parking lot with a single entry and exit gate. Two pairs of sensors$,$ SF and SB$,$ are used at the gate. When a car is between the photo transmitter and the photo receiver, the light is blocked, and the corresponding sensor output is asserted to $1.$ For entrance, when both sensors are unblocked, SB SF$="00".$ As the car enters, Sensor SB is blocked, making SB SF$="10".$ When both sensors are blocked, SB SF$="11".$ As the car moves forward, first Sensor $SB$ is unblocked, resulting in SB SF$="01".$ Then, sensor SF is unblocked, making $SBSF=00".$ For exit, the sensors are blocked in the reverse order.

Design an FSM with two input signals, SB and SF and two output signals, ENTER and EXIT. The ENTER and EXIT signals are asserted one clock cycle when a car enters and exits, respectively.

Write a Verilog module for the FSM and demonstrate its operation using a testbench.

Optional: ENTER and EXIT can be used to increment and decrement the parking occupancy counter. The design should ensure that no car can enter the parking lot if it is full, considering its capacity of $64$ cars.localparam RDYOO$=3\text{'}$d$0,$