Fill the pipeline chart for the following MIPS code. Whenever a stage gets stalled, fill that stage with an S. It is allowed to write and read a register at the same cycle. If data forwarding is allowed, show the forwarding. add $5, $2, $1 lw $3, 4($5) lw $2,0($2) or $3, $5, $3 sw $3,0($5) a) Assume that data forwarding is not allowed. add $5, $2, $1 IF ID EX MEM WB lw $3, 4($5) lw $2, 0($2) or $3, $5, $3 sw $3,0($5) b) Assume that data forwarding is allowed. add $5, $2, $1 IF ID EX MEM WB lw $3, 4($5) lw $2,0($2) or $3, $5, $3 sw $3, 0($5)