Flash Memory

$-$ Your flash memory size is $4$ Tbytes.

$-$ Each block contains $1288$K$-$byte pages.

$-$ Address mapping uses a page$-$level address mapping.

$-$ Read operation takes $50$ usec and write operation takes $200$ usec.

$($a$)$ What's the size of address mapping table entry if we want to address using only a page based address mapping table?

$($b$)$ What's the size of the paged based address mapping table?

The size should be designed as a power of $2.$

$($c$)$ The size of the mapping table is too big and it has to be allocated in the Flash memory. How many blocks we need to store mapping table in Flash?

$($d$)$ For address translation for read and write operation, we need to cache an entry from the mapping table stored in the Flash memory. The cache for the address mapping table has a miss rate of $\backslash (10\backslash \%\backslash ).$ What is the average latency for a read operation?

$-$ Ignore delay for the address translation time if you have a hit in address mapping table cache.

$-$ Address mapping table in Flash is linearly allocated from the known starting address of Flash memory.

$-$ The cache for the address mapping table is a write$-$through cache.

$($e$)$ Consider the same assumption in $($d$).$ What is the average latency for a write operation $($overwrite$)?$