For a $\text{'}$C$\text{'}$ statement as: x$=$a$+$b;

We would typically get an assembly code of:

load r$1,//$load to register r$1,$ the value of the data in memory whose address is a

load r$2,$ b; $//$load to register r$2,$ the value of the data in memory whose address is b

add r$3,$ r$1,$ r$2$; $//$r$3<1+2$

The load time from on$-$chip memory in an SoC through the systerg bus has the following characteristics:

Best Case $20$ clock cycles

Worst Case $125$ clock cycles

The load, and add instructions itself would happen in $1$ clock cycle and there is no instruction fetch related overhead. i$.$e$,$ instructions are in the cpu pipeline already. For

the above assembly code indicating the $\text{'}$C$\text{'}$ statement, What is the BCET $($Best Case Execution Time$)$ and WCET $($Worst Case Execution Time$)$

Select one: