For a direct$-$mapped cache design with a $32-$bit address, the following bits of the address are used to

access the cache.

Tag: $31-10$ Index: $9-5$ Offset: $4-0$

What is the cache block size $($in words$)?$

How many entries does the cache have?

What is the ratio between total bits required for such a cache implementation over the data storage bits?

Starting from power on$,$ the following byte$-$addressed cache references are recorded. Assume the cache

is the one used from problems $3-5.$

Address: $0,4,16,132,232,160,1024,30,140,3100,180,2180$

How many blocks are replaced?

What is the hit ratio?