For a direct$-$mapped cache design with a $64-$bit address, the following bits of the address are used to access the cache.

$($a$)$ What is the cache block size $($in words$)?$

$($b$)$ How many blocks does the cache have?

$($c$)$ What is the ratio between total bits required for such a cache implementation over the data storage bits?

Beginning from power on$,$ the following byte$-$addressed cache references are recorded.

$($d$)$

For each reference, list $(1)$ its tag, index, and offset, $(2)$ whether it is a hit or a miss, and $(3)$ which bytes were replaced $($if any$).$

$($e$)$ What is the hit ratio?

$($f$)$ List the final state of the cache, with each valid entry represented as a record of $.$ For example,

Mem$[0$xC$00]-$Mem$[0$xC$1$F$]>$