For a direct$-$mapped cache design with the $32-$bit

word address, answer the following three sub

questions for each of the following two cache

configurations.

Assume the size of cache line is the same as

the block size. What is the cache line size $($in

words$)?$

How many entries does the cache have?

What is the ratio between total bits required

for such a cache implementation over the

data storage bits? Assume one word is $16$

bits long.