digital logic and computer design

2.) (20 POINTS) Assume a cache with the following parameters: - b: block size given number of words - S: number of sets - N: number of ways - A: number of address bits - word: 4 bytes Using these parameters, give the formula for each item required below. 2.A.) (5 POINTS) Cache capacity C? 2.B.) (5 POINTS) Number of bits required to store the tags? 2.C. (5 POINTS) S and N for a fully associative cache of capacity C words with block size b? 2.D. (5 POINTS) S for a direct mapped cache of size C words and block size b?

3. (30 POINTS) A 16-word cache has the parameters given in Question 2 above. Assume that a program running on this computer executes the following sequence of lw addresses in the exact sequence given: 0x74 0xA0 0x78 0x38C 0xAC 0x84 0x88 0x8C 0x7C 0x34 0x38 0x13C 0x388 0x18C Assuming least recently used (LRU) replacement strategy for associative caches, show the placement of the instruction addresses in cache for each of the following cache design 3.A.) (7.5 POINTS) A direct mapped cache with b=1 word 3.B.) (7.5 POINTS) A fully associative cache with b=2 words 3.C.) (7.5 POINTS) A two-way set associative cache with b=2 words 3.D.) (7.5 POINTS) A direct mapped cache with b=4 words

3. (30 POINTS) A 16-word cache has the parameters given in Question 2 above. Assume that a program running on this computer executes the following sequence of lw addresses in the exact sequence given: 0x74 OxA0 0x78 0x38C 0xAC 0x84 0x88 0x8C 0x7C 0x34 0x38 0x13C 0x388 0x18C Assuming least recently used (LRU) replacement strategy for associative caches, show the placement of the instruction addresses in cache for each of the following cache design 3.A.) (7.5 POINTS) A direct mapped cache with b-l word 3.B.) (7.5 POINTS) A fully associative cache with b-2 words 3.C.) (7.5 POINTS) A two-way set associative cache with b-2 words 3.D.) (7.5 POINTS) A direct mapped cache with b-4 words