Question: For a direct - mapped design with a 6 4 - bit address, the following bits of the address are used to access the cache.

For a direct-mapped design with a 64-bit address, the following bits of the address are used to access the
cache.
a. What the cache line size (in words)?
b. How many entries does the cache have?
c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
For a direct-mapped design with a 64-bit address, the following bits

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