Question: For a direct-mapped cache design with a 32-bit address, the following bits of address are used to access the cache. Tag Index Offset 31-12 11-6

For a direct-mapped cache design with a 32-bit address, the following bits of address are used to access the cache.

Tag

Index

Offset

31-12

11-6

5-0

a, what is the cache block size (in words)?

b, how many entries does this cache have?

c, What is the ratio between total bits required for such a cache implementation over the data storage bits?

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