cache. If it is not possible, explain why.

$5\mathrm{.}5$ For a direct$-$mapped cache design with a $32-$bit address, the following

bits of the address are used to access the cache.

Tag Index Offset

$31109540$

$5\mathrm{.}5\mathrm{.}1[5]<5\mathrm{.}3>$ What is the cache block size $($in words$)?$

$5\mathrm{.}5\mathrm{.}2[5]<5\mathrm{.}3>$ How many entries does the cache have?

$5\mathrm{.}5\mathrm{.}3[5]<5\mathrm{.}3>$ What is the ratio between total bits required for such a

cache implementation over the data storage bits?

Beginning from power on$,$ the following byte$-$addressed cache references are

recorded.

Address

Hex $00041084$ E$8$ A$04001$E $8$C C$1$C B$4884$

Dec $041613223216010243014031001802180$

$5\mathrm{.}5\mathrm{.}4[20]<5\mathrm{.}3>$ For each reference, list $(1)$ its tag, index, and offset, $(2)$

whether it is a hit or a miss, and $(3)$ which bytes were replaced $($if any$).$

$5\mathrm{.}5\mathrm{.}5[10]<5\mathrm{.}3>$ What is the hit ratio?

$3.$a$)$ What is the cache block size $($in words$)?$

$3.$b$)$ How many entries does the cache have?

$3.$c$)$ What is the ratio between total bits required for such a cache implementation over

the data storage bits? Beginning from power on$,$ the following byte$-$addressed cache

references are recorded.

$5\mathrm{.}3\mathrm{.}4.[10]<5\mathrm{.}3,5\mathrm{.}4>$ Generate a series of read requests that have a lower

miss rate on a $32$ KiB two$-$way set associative cache than on the cache

described in Exercise $5\mathrm{.}3\mathrm{.}1.$

$5\mathrm{.}4[15]<5\mathrm{.}3>$ Section $5\mathrm{.}3$ shows the typical method to index a directmapped

cache, specifically $($block address$)$ modulo $($number of blocks in the

cache$).$ Assuming a $64-$bit address and $1024$ blocks in the cache, consider a

different indexing function, specifically $($Block address $[63$:$54]$ XOR Block

address $[53$:$44]).$ Is it possible to use this to index a direct$-$mapped cache? If

so$,$ explain why and discuss any changes that might need to be made to the

cache. If it is not possible, explain why.

$5\mathrm{.}5$ For a direct$-$mapped cache design with a $32-$bit address, the following

bits of the address are used to access the cache.

Tag Index Offset

$31109540$

$5\mathrm{.}5\mathrm{.}1[5]<5\mathrm{.}3>$ What is the cache block size $($in words$)?$

$5\mathrm{.}5\mathrm{.}2[5]<5\mathrm{.}3>$ How many entries does the cache have?

$5\mathrm{.}5\mathrm{.}3[5]<5\mathrm{.}3>$ What is the ratio between total bits required for such a

cache implementation over the data storage bits?

Beginning from power on$,$ the following byte$-$addressed cache references are

recorded.

Address

Hex $00041084$ E$8$ A$04001$E $8$C C$1$C B$4884$

Dec $041613223216010243014031001802180$

$5\mathrm{.}5\mathrm{.}4[20]<5\mathrm{.}3>$ For each reference, list $(1)$ its tag, index, and offset, $(2)$

whether it is a hit or a miss, and $(3)$ which bytes were replaced $($if any$).$

$5\mathrm{.}5\mathrm{.}5[10]<5\mathrm{.}3>$ What is the hit ratio?

$3.$d$)$ For each reference, list $(1)$ its tag, index, and offset, $(2)$ whether it is a hit or a miss,

and $(3)$ which bytes were replaced $($if any$).$

$3.$e$)$ What is the hit ratio?

$3.$f$)$ List the final state of cache, with each valid entry represented as a record of

$.$

$5$