Question: For paging based memory management with a single-level page table : suppose that a system has a 30-bit logical address space and is byte-addressable. The

For paging based memory management with a single-level page table: suppose that a system has a 30-bit logical address space and is byte-addressable. The amount of physical memory is 1MB (i.e., the physical address has 20 bits) and the size of a page/frame is 1K bytes. Assume that each page table entry will use 4 bytes. [Note: you may have the answer in exponential form.]

How many bits are used for offset in a page/frame?

How many bits of logical address are used for page number?

How many pages are in a process logical address space?

How many bits of physical address are used for frame number?

How many frames are in the physical memory?

What information should be stored in a page table entry?

How many entries are in a process page table?

How many bytes would be needed for a page table of a process?

Now assume that the system will have logic address of 18 bits, and the physical address will have 16 bits (supporting up to 64 K bytes). In this system, the size of a frame will be 256 bytes. You will design the two-level page table to reduce the amount of memory required for the page table of a process for this computer.

Illustrate the number of bits in each part of a virtual address in a figure in your design. Analyze the minimum and maximum amount of physical memory required for the page table if a process accesses 4K bytes of virtual memory.

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