5 (Based on COD 5.12) In this exercise, we will examine space/time optimizations for page tables. The following list provides parameters of a virtual memory system. Physical DRAM Installed Virtual Address (bits) Page Size PTE Size (byte) 43 16 GiB 4 KIB 1 5.1 For a single-level page table, how many page table entries (PTEs) are needed? How much physical memory is needed for storing the page table? 5.2 Using a multilevel page table can reduce the physical memory consumption of page tables, by only keeping active PTEs in physical memory. How many levels of page tables will be needed in this case? And how many memory references are needed for address translation if missing in TLB? 5.3 An inverted page table can be used to further optimize space and time. How many PTEs are needed to store the page table? Assuming a hash table implementation, what are the common case and worst case numbers of memory references needed for servicing a TLB miss? 5 (Based on COD 5.12) In this exercise, we will examine space/time optimizations for page tables. The following list provides parameters of a virtual memory system. Physical DRAM Installed Virtual Address (bits) Page Size PTE Size (byte) 43 16 GiB 4 KIB 1 5.1 For a single-level page table, how many page table entries (PTEs) are needed? How much physical memory is needed for storing the page table? 5.2 Using a multilevel page table can reduce the physical memory consumption of page tables, by only keeping active PTEs in physical memory. How many levels of page tables will be needed in this case? And how many memory references are needed for address translation if missing in TLB? 5.3 An inverted page table can be used to further optimize space and time. How many PTEs are needed to store the page table? Assuming a hash table implementation, what are the common case and worst case numbers of memory references needed for servicing a TLB miss