For part D

a. Write MIPs code to perform addition of two unsigned numbers in registers $t1 and $t2 and then verify whether the result has overflowed the 32-bit long destination register $t3. Explain the overflow logic with comments to elaborate upon each line of MIPs code. b. Indicate with a diagram how the same logic can be implemented in hardware. c. Explain with a flow chart and architecture diagram hardware efficient division algorithm may be performed d. Explain why massively parallel implementation of the division algorithm not possible