For problems $6\mathrm{.}1$ through $6\mathrm{.}3$: Suppose the propagation delay of an $8-$bit adder is $0\mathrm{.}8$ns$,$ adder$/$subtractor is $1\mathrm{.}1$ns$,2-$to$-1$ mux is $0\mathrm{.}3$ns$,$ and $4-$to$-1$ mux is $0\mathrm{.}6$ns$.$ Also, assume register setup time $(),$ clock$-$to$-$q $(),$ and clock$-$skew $()$ are all $0\mathrm{.}05$ns$.$