For some reason a keep getting added $2$ like it suppose to be $10+5=15$ but I get $12+5=17$

module alu $($

input $[7$:$0]$ a$,//$ Operand A

input $[7$:$0]$ b$,//$ Operand B

input $[2$:$0]$ opcode, $//$ Operation opcode from FSM

input enable, $//$ Enable signal for ALU operation

output reg $[7$:$0]$ result, $//$ ALU result

output reg div$\_$by$\_$zero $//$ Flag to indicate division by zero

$)$;

$//$ ALU Operations based on opcode

always @$(*)$ begin

div$\_$by$\_$zero $=0$; $//$ Default to no division by zero

result $=8\text{'}$b$0$; $//$ Default to zero result

if $($enable$)$ begin

case $($opcode$)$

$3\text{'}$b$000$: result $=$ a$+$b; $//$ Addition

$3\text{'}$b$001$: result $=$ a$-$b; $//$ Subtraction

$3\text{'}$b$010$: result $=$ a$*$b; $//$ Multiplication

$3\text{'}$b$011$: begin $//$ Division

if $($b $==0)$ begin

result $=8\text{'}$b$0$;

div$\_$by$\_$zero $=1$;

end else begin

result $=$ a$/$b;

end

end

$3\text{'}$b$100$: result $=$ a&b; $//$ AND

$3\text{'}$b$101$: result $=$ a$|$b; $//$ OR

$3\text{'}$b$110$: result $=$ a; $//$ Shift Left

$3\text{'}$b$111$: result $=$ a$>>1$; $//$ Shift Right

default: result $=8\text{'}$b$0$; $//$ Default case

endcase

end

end

endmodule

module alu$\_$tb;

reg $[7$:$0]$ a; $//$ Test Operand A

reg $[7$:$0]$ b; $//$ Test Operand B

reg $[2$:$0]$ opcode; $//$ Test Operation opcode

reg enable; $//$ Test Enable signal

wire $[7$:$0]$ result; $//$ ALU result

wire div$\_$by$\_$zero; $//$ Division by zero flag

$//$ Instantiate the ALU module

alu dut $($

$.$a$($a$),$

$.$b$($b$),$

$.$opcode$($opcode$),$

$.$enable$($enable$),$

$.$result$($result$),$

$.$div$\_$by$\_$zero$($div$\_$by$\_$zero$)$

$)$;

initial begin

$//$ Test cases

$//$ Test Addition

a $=8\text{'}$d$10$; b $=8\text{'}$d$5$; opcode $=3\text{'}$b$000$; enable $=1$;

#$10$;

$//$ Test Subtraction

a $=8\text{'}$d$15$; b $=8\text{'}$d$5$; opcode $=3\text{'}$b$001$; enable $=1$;

#$10$;

$//$ Test Multiplication

a $=8\text{'}$d$3$; b $=8\text{'}$d$4$; opcode $=3\text{'}$b$010$; enable $=1$;

#$10$;

$//$ Test Division $($No Error$)$

a $=8\text{'}$d$20$; b $=8\text{'}$d$4$; opcode $=3\text{'}$b$011$; enable $=1$;

#$10$;

$//$ Test Division $($Division by Zero$)$

a $=8\text{'}$d$20$; b $=8\text{'}$d$0$; opcode $=3\text{'}$b$011$; enable $=1$;

#$10$;

$//$ Test AND

a $=8\text{'}$d$170$; b $=8\text{'}$d$204$; opcode $=3\text{'}$b$100$; enable $=1$; $//$ Binary: a$=10101010,$ b$=11001100$

#$10$;

$//$ Test OR

a $=8\text{'}$d$170$; b $=8\text{'}$d$204$; opcode $=3\text{'}$b$101$; enable $=1$; $//$ Binary: a$=10101010,$ b$=11001100$

#$10$;

$//$ Test Shift Left

a $=8\text{'}$d$15$; b $=8\text{'}$d$0$; opcode $=3\text{'}$b$110$; enable $=1$; $//$ Binary: a$=00001111$

#$10$;

$//$ Test Shift Right

a $=8\text{'}$d$240$; b $=8\text{'}$d$0$; opcode $=3\text{'}$b$111$; enable $=1$; $//$ Binary: a$=11110000$

#$10$;

$//$ Test ALU Disabled

a $=8\text{'}$d$50$; b $=8\text{'}$d$25$; opcode $=3\text{'}$b$000$; enable $=0$;

#$10$;

$finish;

end

endmodule