For the following basic cells, draw the layout and verify the functionality by siulating the extracted netlist. You should strive to get as compact a layout as possible without violating the design rules. The bounding boz of a layout is the smallest rectangle in which your layout can fit. In the lab report you mst report the bounding box area (width x height) of cach cell 1. (10 pts.) Positive Edge Triggered D Flip-flop. Design a D-latch first and then cascade two them with appropriate clock signals 2. (10 pts.) Ful Adder. Look at Subsection 11.2.1 in the text for ideas on optimized full adder implementation 3. (5 pts.) 2-1 AOI (And-OR-Invert) gate implemented as a compound gate with six transistors only. The boolean function is (A V (BAC) 4. (5 pts.) 15-stage Ring Oscillator. Report the clock frequency of the ring oscillator in your report Deliverables (must be uploaded to Canvas by the deadline) Lab report using the template provided. PDF only. Acompressd zip file .tar.gz file) of the design folder of each cell in your lib directory. For the following basic cells, draw the layout and verify the functionality by siulating the extracted netlist. You should strive to get as compact a layout as possible without violating the design rules. The bounding boz of a layout is the smallest rectangle in which your layout can fit. In the lab report you mst report the bounding box area (width x height) of cach cell 1. (10 pts.) Positive Edge Triggered D Flip-flop. Design a D-latch first and then cascade two them with appropriate clock signals 2. (10 pts.) Ful Adder. Look at Subsection 11.2.1 in the text for ideas on optimized full adder implementation 3. (5 pts.) 2-1 AOI (And-OR-Invert) gate implemented as a compound gate with six transistors only. The boolean function is (A V (BAC) 4. (5 pts.) 15-stage Ring Oscillator. Report the clock frequency of the ring oscillator in your report Deliverables (must be uploaded to Canvas by the deadline) Lab report using the template provided. PDF only. Acompressd zip file .tar.gz file) of the design folder of each cell in your lib directory