CMOS VLSI Design Lab 4

For the following basic cells, draw the layout and verify the functionality by simulating the extracted netlist. You should strive to get as compact a layout as possible without violating the design rules. The bounding box of a layout is the smallest rectangle in which your layout can fit. In the lab report you must report the bounding box area (width x height) of each cell.

1. (10 pts.) Positive Edge Triggered D Flip-flop. Design a D-latch first and then cascade two them with appropriate clock signals.

2. (10 pts.) Full Adder. Look at Subsection 11.2.1 in the text for ideas on optimized full adder implementation.

3. (5 pts.) 2-1 AOI (And-OR-Invert) gate implemented as a compound gate with six transistors only. The boolean function is (A(BC))'.

4. (5 pts.) 15-stage Ring Oscillator. Report the clock frequency of the ring oscillator in your report.

Tips

You can use the pre-drawn cells for PMOS (epm) and NMOS (enm) cells in the c5 library as thestarting point for your layouts.

Include all SPICE netlists, simulation waveforms. For simulation results, zoom in/out appropriately so that we can clearly see the input stimuli and the output response.