For the following instructions:

$```$

A: load R$1,$ e$($R$10)//$ R$1=$ MEM$[$R$10+0]$

B: sub R$2,$ R$3,$ R$4//$ R$2=$ R$3-$ R$4$

C: mul R$5,$ R$1,$ R$2//$ R$5=$ R$1*$ R$2$

D: beqz R$2,$ X $//$ if $($R$2==0)$ jump to X

E: store R$6,\backslash$theta$($R$11)//$ Mem$[$R$11+0]=$ R$6$

X: store R$5,0($R$11)//$ Mem$[$R$11+0]=$ R$5$

$```$

Assume that branch D$\text{'}$s true outcome is Taken.

a$)$ Fill in the pipeline timing diagram for the instructions. Assume a basic DLX $5-$stage pipeline $($F$,$ D$,$ X$,$ M$,$ W$,$ which stands for Fetch, Decode, Execute, Memory, Write back$).$ Use the following additional assumptions:

$-$ No forwarding$/$bypassing logic

$-$ No branch prediction

$-$ Branch outcome is resolved at the M stage

$-$ Write back to register takes up the entire pipeline stage

Use the following table to express your answer. For each instruction in the table, indicate which clock cycle the instruction enters a particular pipeline stage. For example, for instruction A $,$ it is fetched at cycle $1,$ decoded at cycle $2,$ executed at cycle $3,$ enters memory stage at cycle $4,$ and writes back its result at cycle $5.$ If an instruction is not processed in the pipeline, put $"-"($without quotation marks$)$ in all cells for the instruction.

Hint: I advise that you start by filling in pipeline timing diagram similar to the one shown below, then take the information from there and enter them into the table above.

Clock cycle