Question: For the given Verilog procedure of a multi - function register, which control input has the highest priority? always @ ( posedge clk ) begin

For the given Verilog procedure of a multi-function register, which control input
has the highest priority?
always @(posedge clk) begin
if (rst ==1)
R =4'b0000;
else if (ld ==1)
R = I;
else if (shr ==1) begin
R[0]= R[1];
R[1]= R[2];
R[2]= R[3];
R[3]= Shr_in;
end
else if (shl ==1) begin
R[3]<= R[2];
R[2]= R[1];
R[1]= R[0];
R[0]= Shl_in;
end
end
a. ld
b. shr
c. shl
d. shr_in

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