For the implementation of the Tiny instruction set architecture sketched in the slides for day 17 of class:

ALU instructions require Load / store instructions require Ordinary unconditional branch instructions require Subprogram call instructions require Conditional branch instructions (not taken) require Conditional branch instructions (taken) require

4 cycles to execute 6 cycles to execute 4 cycles to execute 5 cycles to execute 4 cycles to execute 5 cycles to execute

For an important suite of applications, half of the instructions are found to be ALU instructions, 20% loads, 10% stores, and 20% branches. Of the branches, one tenth are sub-program calls (unconditional branches that save the return address rT is not $0), three tenths are ordinary unconditional branches, two tenths are conditional branch instructions where the branch does not end up being taken, and four tenths are conditional branches that are taken.

2)Suppose that, in a radically different implementation of the TINY ISA, every instruction requires six cycles (3 to fetch and 3 to execute), but the execution phase of one instruction can be overlapped with the fetch phase of the next instruction. Since two instructions are being processed at once, the effective CPI for this implementation is 3 cycles per instruction. What is the speed up of this implementation over that of #1?