Question: For the Verilog code below: moduleExam2(f, g, x); input [2:theta] x; output f, g wire [2:theta] nx= nx; -x; assign f = g & nx[1];

For the Verilog code below: moduleExam2(f, g, x); input [2:theta] x;

For the Verilog code below: moduleExam2(f, g, x); input [2:theta] x; output f, g wire [2:theta] nx= nx; -x; assign f = g & nx[1]; assign g = nx[2] & x[1]^nx[theta] endmodule a. If the initial values for the ports are f = 0, g = 0, x = 000 find the new output values. b. Draw the circuit. For the Verilog code below: moduleExam2(f, g, x); input [2:theta] x; output f, g wire [2:theta] nx= nx; -x; assign f = g & nx[1]; assign g = nx[2] & x[1]^nx[theta] endmodule a. If the initial values for the ports are f = 0, g = 0, x = 000 find the new output values. b. Draw the circuit

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