For these questions, you may use the 74LS138 decoder (given, image courtesy Texas Instruments) and AND, OR, and NOT gates for your decoding logic. Note that the notation for the decoder enables is different than what we discussed in class, with the given decoder having one active-high enable (G1), and two active low enables (G2A and G2B) 3. The processor used in this question uses a 8-bit address bus. Using the same 2k x 8 devices as in the previous question, implement a memory structure that can store.... 6 kbytes of data using an 8-bit data bus. The starting address of this 10- kbyte structure is 0x06000 a. ?3 14DY1 Y77 Y5 16 kbytes of data using an 8-bit data bus. The starting address of this 16- kbyte structure is 0xOC000 b. G285 1Y3