Formally specify,

Design

$,$

implement

and verify

a

Verilog

module

that will

output your Brunel student number one digit every X$1,$ X$2,$ or X$3$ clock pulses

$,$

depending on external input

s

$.$

Once the complete sequence is outputted it should

stop at the last digit.

Each digit is to be presented in pure unsigned binary. It

should be possible to

$$

hold

$$

the value of the current digit by the use of a

n

external input

$($Enable$)$

$.$

The Hold function shou

ld be a synchronous function.

It

should also be possible to reset the ID generator back to the start digit

$($i$.$e$.$ the

Most Significant digit$)$

of the ID number

by the use of an external input

$($Reset$)$

$.$

Identify and explain any design decisions that are neede

d$.$

Hint: it is possible to design an initial

generator

and add the additional features

at a later stage.

i$.$e$.$ don$$t try to implement the system in one go