Formally specify, design, implement and verify a Verilog module that will

output $2025122$ one digit every $1,4,$ or $6$ clock pulses,

depending on external inputs. Once the complete sequence is outputted it should

stop at the last digit. Each digit is to be presented in pure unsigned binary. It

should be possible to $$hold$$ the value of the current digit by the use of an

external input $($Enable$).$ The Hold function should be a synchronous function. It

should also be possible to reset the ID generator back to the start digit $($i$.$e$.$ the

Most Significant digit $(2))$ of the ID number by the use of an external input $($Reset$).$

Identify and explain any design decisions that are needed.

Hint: it is possible to design an initial generator and add the additional features

at a later stage. i$.$e$.$ don$$t try to implement the system in one go$!$

Binary to BCD encoder

Formally specify, design and verify the encoder to convert pure binary to the

given weighted BCD code. This module should be implemented in functional

level Verilog. Hint: a case statement might be a sensible$.$

Parity Generator:

Formally specify, design and verify a gate level Verilog module that will output

both the odd and even parity of each weighted BCD digit generated.

Identify any ambiguity in the specification and make sensible design choices

where necessary. Generate a formal specification for each module $($partition$)$

before you try to implement your design. Implement each design partition and

test$/$verify it$.$ Finally, integrate each partition into the overall system using a

gate level module.