The following figure and table are the process address space and machine state when CPU is...

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The following figure and table are the process address space and machine state when CPU is about to fetch and execute instruction at Ox80483dd push %ebp. Please describe what changes will be made to (1) stack segment and (2) x86 registers after CPU executes the push instruction. You can reference to x86 instruction sets which being used in class if needed. Text segment 080483dd <bar>: 80483dd: 80483de: 8048360: push mov sub tebp Ngap, abg $0x10, tesp Stack segment 4 (gdb) info registers eax 0x1 ecx edx ebx esp ebp esi edi eip eflags CS SS ds es fs gs Øxe3d3653b 0xffffcfb4 0xf7fd4000 0xffffcf8c 0x0 0x0 0x0 0x80483dd 0x246 0x23 0x2b 0x2b 0x2b 0x0 0x63 [ PF ZF IF ] 080483dd <bar>: 80483dd: 80483de: 8048300: 80483e3: 8048306: 80483e9: 80483eb: 80483ee: 8048310: 8048313: 80483f7: 80483fa: 80483fb: 080483fc <main>: 80483fc: 80483fd: 80483ff: 8048402: 8048409: Text segment 8048410: 8048417: 804841a: 804841e: 8048421: 8048425: 8048428: 804842b: 8048430: 8048433: 8048437: 804843A: 804843b: push mov sub mov mov add mov add mov addl mov leave ret push mov sub moy BRYZ mox mov mov mov mov mov mov call mov addl mov leave ret tebp esp, lebp $0x10, Resp Oxc (tebp), teax Ox8 (Sebp), Bedx Seax, Sedx 0x10 (Bebp), Seax Sedx, Seax Seax,-0x4 (Sebp) $0x6,-0x4 (Sebp) -0x4 (bebp), teax Sebp teap, kebp $0x1c, lesp $0x1,-0x4 (1ebp) 50x2,-0x8 (1ebp) 50x3,-0xc (tebp) -Oxe (ebp), *gax beax, 0x8 (esp) -0x8 (Sebp), teax Seax, 0x4 (sesp) -Qx4 (igbp), gAX gax, (ap) 80483dd <bar> Seax, -0x4(lebp) 50x5,-0x4 (tebp) -0x4 (Sebp), Seax Oxffffcf8c Oxffffcf88 Oxffffcf84 Oxffffcf80 Oxffffefle Oxffffcf78 Oxffffcf74 Oxffffcf70 Oxffffcf6c Oxffffcf68 Oxffffet64 Oxffffcf60 Oxffffef5c Oxffffcf58 Oxffffcf54 Oxffffef50 Oxffffcf40 Oxfffff48 Oxffffc144 OXFFFICE40 Oxftficf3c Oxffffor38 Oxffff034 Stack segment The following figure and table are the process address space and machine state when CPU is about to fetch and execute instruction at Ox80483dd push %ebp. Please describe what changes will be made to (1) stack segment and (2) x86 registers after CPU executes the push instruction. You can reference to x86 instruction sets which being used in class if needed. Text segment 080483dd <bar>: 80483dd: 80483de: 8048360: push mov sub tebp Ngap, abg $0x10, tesp Stack segment 4 (gdb) info registers eax 0x1 ecx edx ebx esp ebp esi edi eip eflags CS SS ds es fs gs Øxe3d3653b 0xffffcfb4 0xf7fd4000 0xffffcf8c 0x0 0x0 0x0 0x80483dd 0x246 0x23 0x2b 0x2b 0x2b 0x0 0x63 [ PF ZF IF ] 080483dd <bar>: 80483dd: 80483de: 8048300: 80483e3: 8048306: 80483e9: 80483eb: 80483ee: 8048310: 8048313: 80483f7: 80483fa: 80483fb: 080483fc <main>: 80483fc: 80483fd: 80483ff: 8048402: 8048409: Text segment 8048410: 8048417: 804841a: 804841e: 8048421: 8048425: 8048428: 804842b: 8048430: 8048433: 8048437: 804843A: 804843b: push mov sub mov mov add mov add mov addl mov leave ret push mov sub moy BRYZ mox mov mov mov mov mov mov call mov addl mov leave ret tebp esp, lebp $0x10, Resp Oxc (tebp), teax Ox8 (Sebp), Bedx Seax, Sedx 0x10 (Bebp), Seax Sedx, Seax Seax,-0x4 (Sebp) $0x6,-0x4 (Sebp) -0x4 (bebp), teax Sebp teap, kebp $0x1c, lesp $0x1,-0x4 (1ebp) 50x2,-0x8 (1ebp) 50x3,-0xc (tebp) -Oxe (ebp), *gax beax, 0x8 (esp) -0x8 (Sebp), teax Seax, 0x4 (sesp) -Qx4 (igbp), gAX gax, (ap) 80483dd <bar> Seax, -0x4(lebp) 50x5,-0x4 (tebp) -0x4 (Sebp), Seax Oxffffcf8c Oxffffcf88 Oxffffcf84 Oxffffcf80 Oxffffefle Oxffffcf78 Oxffffcf74 Oxffffcf70 Oxffffcf6c Oxffffcf68 Oxffffet64 Oxffffcf60 Oxffffef5c Oxffffcf58 Oxffffcf54 Oxffffef50 Oxffffcf40 Oxfffff48 Oxffffc144 OXFFFICE40 Oxftficf3c Oxffffor38 Oxffff034 Stack segment

Answer rating: 100% (QA)

After the CPU executes the push ebp instruction at 0x80483dd the following changes ... View the full answer