General Assignment Specification 1. You are to write a memory simulator for a system containing a two-level memory hierarchy associative cache mapping. The simulator must support various set-associativities; various replacem policies including least-recently-used (LRU) and FIFO; and the write-back write policy will be prompted from the user and read from a file supplied by the user. Input file specifications are described below. The simulator must be able to calculate various operational and performmance characteristics (described below) of different memory config using set- urations for your embedded system Requirements he simulator must query the user for the memory configuration and the name of an input file containing a sequence of memory references/addresses generated by the CPU. Using this information, the program must compute the following l) the number of address lines required, 2) the size of the offset field of the memory address 3) the size of the index field of the memory address, 4) the size of the tag field of the memory address 5) the total size of the cache memory 6) a table consisting of the main memory (mm) block number, the cache memory (cm) block number, the cm set number, and the hitmiss "status" of each memory reference in the sequence 7 the highest possible hit rate for the sequence of references, 8) the actual hit rate for the sequence of references, and 9) a table showing the final "status" of the cache memory including the contents of each cache field for each cache block. Your program should also prompt the user to continue with the analysis of a new memory exit after each "run configuration on This assignmen assignment. You are welcome to write your simulator on any lab PC or your own laptop. However must be done in the Embedded Systems Lab (2005 SERC) t must be written in the C programming language. No Arduino hardware is required for this You are responsible for demonstrating the program to the TA on or before the due date. This assignment is an independent assignment. Therefore, no teaming is al lowed. General Assignment Specification 1. You are to write a memory simulator for a system containing a two-level memory hierarchy associative cache mapping. The simulator must support various set-associativities; various replacem policies including least-recently-used (LRU) and FIFO; and the write-back write policy will be prompted from the user and read from a file supplied by the user. Input file specifications are described below. The simulator must be able to calculate various operational and performmance characteristics (described below) of different memory config using set- urations for your embedded system Requirements he simulator must query the user for the memory configuration and the name of an input file containing a sequence of memory references/addresses generated by the CPU. Using this information, the program must compute the following l) the number of address lines required, 2) the size of the offset field of the memory address 3) the size of the index field of the memory address, 4) the size of the tag field of the memory address 5) the total size of the cache memory 6) a table consisting of the main memory (mm) block number, the cache memory (cm) block number, the cm set number, and the hitmiss "status" of each memory reference in the sequence 7 the highest possible hit rate for the sequence of references, 8) the actual hit rate for the sequence of references, and 9) a table showing the final "status" of the cache memory including the contents of each cache field for each cache block. Your program should also prompt the user to continue with the analysis of a new memory exit after each "run configuration on This assignmen assignment. You are welcome to write your simulator on any lab PC or your own laptop. However must be done in the Embedded Systems Lab (2005 SERC) t must be written in the C programming language. No Arduino hardware is required for this You are responsible for demonstrating the program to the TA on or before the due date. This assignment is an independent assignment. Therefore, no teaming is al lowed