Given a $16-$byte cache $($byte$-$addressable, initially empty$)$ and a sequence of

access addresses: $(2)10,(14)10,(0)10,(17)10,(12)10,(3)10,$ please derive the

corresponding hit$/$miss sequence for each of the following cache designs.

There is one question for each design. Choose correct statement$($s$)$ below:

$($a$)8$ bytes per block, direct$-$mapped has three hits.

$($b$)8$ bytes per block, direct$-$mapped has more than two misses.

$($c$)4$ bytes per block, $2-$way set associative has three hits

$($d$)4$ bytes per block, $2-$way set associative has more than two misses.