Given a computer using a byte$-$addressable virtual memory system with a two$-$entry TLB$,$ a $2-$way set

associative cache, and a page table for a process P$.$ Assume cache blocks of size $8$ bytes. Assume pages of

size $16$ bytes and a main memory of $4$ frames. Assume the following TLB and page table for Process P:

How many bits are in a physical address?

$6$

$8$

$10$

$12$

None of the above