Given a virtual memory system with a TLB, a cache, and a page table. Assume the following: A TLB hit requires 5ns, a cache hit requires 10ns, a memory reference requires 25ns A disk reference requires 200ms (includes updating the page table, cache, and TLB) The TLB hit ratio is 90%, the cache hit rate is 95%, the page fault rate is .001% On a TLB or cache miss, the time required for access includes a TLB and/or cache update, but the access is not restarted On a page fault, the page is fetched from disk, all updates are performed but the access is restarted All references are sequential (no overlap, nothing done in parallel) For each of the following, indicate whether or not it is possible. If it is possible, specify the time required for accessing the requested data.

a. TLB hit, cache hit

b. TLB miss, page table hit, cache hit

c. TLB miss, page table hit, cache miss

d. TLB miss, page table miss, cache hit

e. TLB miss, page table miss