Question: Given that wire [3:0] X; wire [7:0] Y; wire [11:0] Z; write a Verilog statement that concatenates X and Y and puts the result in

Given that wire [3:0] X;

wire [7:0] Y;

wire [11:0] Z;

write a Verilog statement that concatenates X and Y and puts the result in Y. X should go in the lower order bits of Z.

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