Question: Verilog Language, Given these definitions wire [3:0] var1; wire [7:0] var2; wire [11:0] var3; write a statement that concatenates var1 and var2 and puts that

Verilog Language, Given these definitions wire [3:0] var1; wire [7:0] var2; wire [11:0] var3; write a statement that concatenates var1 and var2 and puts that in var3, var1 should go in the low order bits

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