Given the following assumptions, pipeline the following program:

$$ Integer Unit $($loads$,$ stores and integer arithmetic$)$ takes $1$ clock cycle

$$ FP Adder takes $2$ clock cycles$-$ Subtraction uses the adder

$$ FP Multiplier takes $10$ Clock cycles$$ FP Divider takes $40$ Clock cycles

$$ Full forwarding

$$ Register can be written in first half of cycle and read in second half of cycle

LD F$634($R$2)$

ADD F$6$ F$6$ F$2$

MUL F$4$ F$6$ F$3$

SUB F$7$ F$4$ F$2$

Make sure you enter your answers as shown below:

Stalls $-$ STALL

Fetch Stage $-$ IF

Decode stage $-$ ID

Memory $-$ MEM

Write Back $-$ WB

Execution stage:

Integer ALU $-$ EX

FP Adder $-$ A#

where # represents the number of the stage we are in for example A$1$

FP Multiplier $-$M#

where # represents the number of the stage we are in for example M$1$

FP Divider $-$D#

where # represents the number of the stage we are in for example D$1$