Given the following MIPS assembly code segment, at the specified byte memory addresses:

860		addi	$16, $0, 50
864		addi	$17, $0, -22
868		slt	$10, $16, $17
872		bne	$10, $0, next
876		or	$21, $16, $17
880		sw	$21, 24($20)
884	next:	lw	$22, 12($20)

running on a multi-cycle MIPS processor, with the first ADDI starting execution in cycle 1.

a) In cycle 2, what is the decimal value of the ALUSrcB control signal ?

b) Still in cycle 2, what decimal value will be input to the ALU as the second operand? (chosen by the ALUSrcB setting)

c) In cycle 7, what is the decimal value of the ALUSrcB control signal ?

d) In cycle 7, what is the decimal value will be saved to the ALUout register?

e) In cycle 12, what is the decimal value of the RegDst control signal ?

f) Still in cycle 12, what decimal value will sent to the Write Data input of the Register File ?

g) In cycle 18, what is the decimal value of the IRwrite control signal ?

h) Still in cycle 18, what decimal value will be sent to the Control Unit ?