Given the Logic Function: Y= (A + B + C) * (A' + B' +C) * (A + B' + C) (a) Generate a truth table for the function (rows of table must be in numerical order) (b) Using the basic gates: NOT, AND, OR, implement the function at the gate level (not transistor level). (c) If AND gates have a delay of 2.5fs, OR gates have a delay of 3fs, and Inverters have a delay of 1fs, what is the total delay of your circuit