Given the Logic Function: Y= (A + B + C) * (A + B +C) * (A + B + C)

(A) Using the basic gates: NOT, AND, OR, implement the function at the gate level (not transistor level). (DO NOT MINIMIZE LOGIC HERE)

(B) From the truth table of the logic function, implement the fuction at the gate level using a PLA

(C) If AND gates have a delay of 2.5fs, OR gates have a delay of 3fs, and Inverters have a delay of 1fs, what is the total delay of the PLA implementation?

(D) In terms of speed, which implementation (PLA or the gate level implementation in (A)) is better? In terms of area on chip, which implementation is better?

(E) Use Karnaugh map (k-map) to minimize the logic of the function

(F) Implement your reduced function using basic gates

(G) Implement the simplest design of the reduced function in CMOS (the transistor level).