Given the Verilog description below, draw the gate level circuit and give a test vector that tests each of the following faults so that the faults are visible at the module output. Use the given spaces to enter a viable test vector for each fault. 1 2 3 module exam_logic(a, f): input a[0:4]; output f; nor nro (x1, a[0], a [1]); nor nrl (x2, a[2], a[3]); nand nal (x3, x1, x2); not no (x4, a [4]); nand na2 (f,x4, x3); endmodule 7 8 9 - a) x1 SA/O a[0] = _, a[1] = -, a[2] = a[3] = a[4] = b) f SA/1 a[0] = , a[1] = _, a[2] = , a[3] = _, a[4] = Given the Verilog description below, draw the gate level circuit and give a test vector that tests each of the following faults so that the faults are visible at the module output. Use the given spaces to enter a viable test vector for each fault. 1 2 3 module exam_logic(a, f): input a[0:4]; output f; nor nro (x1, a[0], a [1]); nor nrl (x2, a[2], a[3]); nand nal (x3, x1, x2); not no (x4, a [4]); nand na2 (f,x4, x3); endmodule 7 8 9 - a) x1 SA/O a[0] = _, a[1] = -, a[2] = a[3] = a[4] = b) f SA/1 a[0] = , a[1] = _, a[2] = , a[3] = _, a[4] =