given the VHDL code and testebench of a MUX simulate the design and print out the waveform( explain why its works or not), and trasnlate the program into an equivalent verilog implementation. Provide waveform for verilog simulation also

- Multiplexor is a device to select different - inputs to outputs. we use 3 bits vector to - describe its 1/O ports 1 ibrary ieee; use 1eee.std logic_1164.a11; entity Mux is port ( 13: in std_logic_vector (2 downto 0): 12. In std logic vector (2 downto 0): 11: in std logic_vector (2 downto 0); 10: in std logic_vector {2 downto 0} : 5: In std logie_vector (1 downto 0); 0: out std_logic_vector (2 downto 0) ): end Mux; architecture behvi of Mux is begin process (13,12,11,10,S) begin end case; end process; end behvi: architecture behv2 of Mux is begin -. use when.. else statement 0