Gray Code

Consider a $4-$bit binary counter currently storing the decimal number $7$; its internal binary representation is $0111.$ When the count rolls over to $8,$ the internal bits become $1000,$ requiring all $4$ bits to switch simultaneously. Although numbers $7$ and $8$ have a distance of $1$ between them, the binary representations bear little resemblance to each other. This phenomenon extends to n$-$bits: whenever the number rolls over from $2$n $1$ to $2$n$,$ n $+1$ bits must change state at once. In electronics, current is drawn whenever a bit transitions from low to high or vice versa; however, power consumption is minimized when the state of each bit is preserved. Consequently, it might be desirable to develop a design that minimizes the amount of bit flips during a $"+1"$ counter operation. Furthermore, numerous simultaneous bit flips can introduce errors into the circuit.

Building on this concept, you will implement a Gray Code counter based on the principles established by Frank Gray $[1].$ Examine the numbers presented in Table $1,$ comparing their binary and Gray Codes in detail. Notice that the Gray Code necessitates only a single bit to transition between states at each increment.

In binary and Gray Code systems, the counts of zeros and ones at each bit position are identical and comprise half of the total number of decimal values that can be represented within a given range. For example, in the $4-$bit scenario, there are eight logic$-$level lows and eight logic$-$level highs for all bits, differing only in their order of arrangement. Therefore, there is a pattern to generate a n$-$bit Gray Code counter. Figure out how to design a circuit that increments in Gray Code domain.

According to the described operation:

$[5]$ Describe the algorithm to generate n$-$bit Gray Code recursively.

$[5]$ Write a SystemVerilog module for a $4-$bit Gray Code up$-$counter with enable signal and parallel load. Prepare a testbench for it to verify functionality.

$[5]$ Write a SystemVerilog module for a $8-$bit Gray Code up$-$counter with enable signal and parallel load. Prepare a testbench for it to verify functionality.