Hello, need help with Computer Architecture lab. Unsure how to implement the reset signal. Program used is Model Sim.

Lab description:

My Code:

Lab 5: Design and implement the positive edge triggered D flip flop with RESET signal using VHDL/Verilog. When RESET=1 the flip flop should be cleared. RESET does not depend on the CLOCK signal. This is called Asynchronous RESET. When RESET=0 the flip flop should store the input. The output follows the input when CLOCK is 1. library ieee; use ieee.std_logic_1164.all; 2 3 4 5 entity dc is port (d :in bit;clk: inout bit; q:out bit); end dc; 7 architecture behav of dC is begin pl: process (clk, d) begin if (clk='l') then q