help please

3. Design a circuit with 1 top module and 4 sub-modules. a). Top module with 4 inputs x1,x2,x3 and s, and 7 outputs a, b, c,..., and g for 7 seg LED display. If s=0, display the sum of the three numbers (0 to 3); if s=1, display the majority of the numbers from x1 to x3 on the LED (0 or 1). b). Draw the circuit block diagram for the problem with 4 sub-modules below 2-1 mux mux2; 3 single bit adder add3; 3 person voting machine vote3, 2bit 7 seg display seg7 (to display decimal 0 to 3 for the two bits). Hints: two instances of the mux2 are used. c) Write the hierarchical Verilog codes for the top module and every sub-module with each module in a separate .v file. You may need to test each sub-module individually first using the functional simulation before testing of the top module