Here you are asked to implement basic modules in SystemVerilog.

Each component should be implemented as a Verilog module in a separate .sv file. Each module should have its own testbench also implemented in a separate .sv file, which you will run and explain during the checkoff or in your comments.

The inputs provided by the testbench should demonstrate that your module behaves as expected. Coding style is important: use comments to clearly identify the different modules and organize your code in a readable way.

Components to implement: 1) 1-bit Half adder

inputs (1-bit each) are A and B (addends)

outputs (1-bit each) are C_o (carry out) and S (sum)

2) 1-bit Full adder

same, but inputs now A, B, and C_i (carry-in)

3) 3-bit Majority voter

three 1-bit inputs, A, B and C.

1-bit output OUT = the most frequent input.

For example if A=0, B=1, C=0, then OUT is 0.

If A=1, B=1, C=0, then OUT is 1)

This is how we build a full adder's carry-out logic

4) n-bit Equality comparator

two n-bit inputs A and B

1-bit output OUT

If A and B are equal, OUT is 1, otherwise is 0.

5) 4:1 MUX

four n-bit data inputs A, B, C, D

2-bit control SEL

n-bit output OUT

SEL values 0 through 3 select A through D